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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8036/ad8037 and large-signal bandwidths and ultralow distortion. the ad8036 achieves C66 dbc at 20 mhz, and 240 mhz small- signal and 195 mhz large-signal bandwidths. the ad8036 and ad8037s recover from 2 clamp overdrive within 1.5 ns. these characteristics position the ad8036/ad8037 ideally for driving as well as buffering flash and high resolution adcs. in addition to traditional output clamp amplifier applications, the input clamp architecture supports the clamp levels as addi- tional inputs to the amplifier. as such, in addition to static dc clamp levels, signals with speeds up to 240 mhz can be applied to the clamp pins. the clamp values can also be set to any value within the output voltage range provided that v h is greater that v l . due to these clamp characteristics, the ad8036 and ad8037 can be used in nontraditional applications such as a full-wave rectifier, a pulse generator, or an amplitude modula- tor. these novel applications are only examples of some of the diverse applications which can be designed with input clamps. the ad8036 is offered in chips, industrial (C40 c to +85 c) and military (C55 c to +125 c) package temperature ranges and the ad8037 in industrial. industrial versions are available in plastic dip and soic; mil versions are packaged in cerdip. C4 C3 C2 C1 0 1 2 3 4 4 3 2 1 0 C1 C2 C3 C4 input voltage C volts output voltage C volts v l = C3v v l = C2v v l = C1v v h = 1v v h = 2v v h = 3v ad8036 figure 1. clamp dc accuracy vs. input voltage features superb clamping characteristics 3 mv clamp error 1.5 ns overdrive recovery minimized nonlinear clamping region 240 mhz clamp input bandwidth 6 3.9 v clamp input range wide bandwidth ad8036 ad8037 small signal 240 mhz 270 mhz large signal (4 v p-p) 195 mhz 190 mhz good dc characteristics 2 mv offset 10 m v/ 8 c drift ultralow distortion, low noise C72 dbc typ @ 20 mhz 4.5 nv/ ? hz input voltage noise high speed slew rate 1500 v/ m s settling 10 ns to 0.1%, 16 ns to 0.01% 6 3 v to 6 5 v supply operation applications adc buffer if/rf signal processing high quality imaging broadcast video systems video amplifier full wave rectifier functional block diagram 8-lead plastic dip (n), cerdip (q), and so packages 1 2 3 4 8 7 6 5 ad8036/ ad8037 nc Cinput +input Cv s +v s output (top view) nc = no connect v l v h low distortion, wide bandwidth voltage feedback clamp amps product description the ad8036 and ad8037 are wide bandwidth, low distortion clamping amplifiers. the ad8036 is unity gain stable. the ad8037 is stable at a gain of two or greater. these devices al- low the designer to specify a high (v ch ) and low (v cl ) output clamp voltage. the output signal will clamp at these specified levels. utilizing a unique patent pending clampin? input clamp architecture, the ad8036 and ad8037 offer a 10 im- provement in clamp performance compared to traditional out- put clamping devices. in particular, clamp error is typically 3 mv or less and distortion in the clamp region is minimized. this product can be used as a classical op amp or a clamp am- plifier where a high and low output voltage are specified. the ad8036 and ad8037, which utilize a voltage feedback ar- chitecture, meet the requirements of many applications which previously depended on current feedback amplifiers. the ad8036 and ad8037 exhibit an exceptionally fast and accurate pulse response (16 ns to 0.01%), extremely wide small-signal clampin is a trademark of analog devices, inc. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999
ad8036/ad8037Cspecifications electrical characteristics rev. a C2C ( v s = 5 v; r load = 100 w ; a v = +1 (ad8036); a v = +2 (ad8037), v h , v l open, unless otherwise noted) ad8036a ad8037a parameter conditions min typ max min typ max units dynamic performance bandwidth (C3 db) small signal v out 0.4 v p-p 150 240 200 270 mhz large signal 1 8036, v out = 2.5 v p-p; 8037, v out = 3.5 v p-p 160 195 160 190 mhz bandwidth for 0.1 db flatness v out 0.4 v p-p 8036, r f = 140 w ; 8037, r f = 274 w 130 130 mhz slew rate, average +/C v out = 4 v step, 10C90% 900 1200 1100 1500 v/ m s rise/fall time v out = 0.5 v step, 10C90% 1.4 1.2 ns v out = 4 v step, 10C90% 2.6 2.2 ns settling time to 0.1% v out = 2 v step 10 10 ns to 0.01% v out = 2 v step 16 16 ns harmonic/noise performance 2nd harmonic distortion 2 v p-p; 20 mhz, r l = 100 w C59 C52 C52 C45 dbc r l = 500 w C66 C59 C72 C65 dbc 3rd harmonic distortion 2 v p-p; 20 mhz, r l = 100 w C68 C61 C70 C63 dbc r l = 500 w C72 C65 C80 C73 dbc 3rd order intercept 25 mhz +46 +41 dbm noise figure r s = 50 w 18 14 db input voltage noise 1 mhz to 200 mhz 6.7 4.5 nv ? hz input current noise 1 mhz to 200 mhz 2.2 2.1 pa ? hz average equivalent integrated input noise voltage 0.1 mhz to 200 mhz 95 60 m v rms differential gain error (3.58 mhz) r l = 150 w 0.05 0.09 0.02 0.04 % differential phase error (3.58 mhz) r l = 150 w 0.02 0.04 0.02 0.04 degree phase nonlinearity dc to 100 mhz 1.1 1.1 degree clamp performance clamp voltage range 2 v ch or v cl 3.3 3.9 3.3 3.9 v clamp accuracy 2 overdrive, v ch = +2 v, v cl = C2 v 3 10 3 10 mv t min Ct max 20 20 mv clamp nonlinearity range 3 100 100 mv clamp input bias current (v h or v l ) 8036, v h, l = 1 v; 8037, v h, l = 0.5 v 40 60 50 70 m a t min Ct max 80 90 m a clamp input bandwidth (C3 db) v ch or v cl = 2 v p-p 150 240 180 270 mhz clamp overshoot 2 overdrive, v ch or v cl = 2 v p-p 1 5 1 5 % overdrive recovery 2 overdrive 1.5 1.3 ns dc performance 4 , r l = 150 w input offset voltage 5 27 27mv t min Ct max 11 10 mv offset voltage drift 10 10 m v/ c input bias current 410 39 m a t min Ct max 15 15 m a input offset current 0.3 3 0.1 3 m a t min Ct max 55 m a common-mode rejection ratio v cm = 2 v 66 90 70 90 db open-loop gain v out = 2.5 v 48 55 54 60 db t min Ct max 40 46 db input characteristics input resistance 500 500 k w input capacitance 1.2 1.2 pf input common-mode voltage range 2.5 2.5 v output characteristics output voltage range, r l = 150 w 3.2 3.9 3.2 3.9 v output current 70 70 ma output resistance 0.3 0.3 w short circuit current 240 240 ma power supply operating range 3.0 5.0 6.0 3.0 5.0 6.0 v quiescent current 20.5 21.5 18.5 19.5 ma t min Ct max 25 24 ma power supply rejection ratio t min Ct max 50 60 56 66 d b notes 1 see max ratings and theory of operation sections of data sheet. 2 see max ratings. 3 nonlinearity is defined as the voltage delta between the set input clamp voltage (v h or v l ) and the voltage at which v out starts deviating from v in (see figure 73). 4 measured at a v = 50. 5 measured with respect to the inverting input. specific ations subject to change without notice.
ad8036/ad8037 rev. a C3C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although these devices feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 v voltage swing bandwidth product . . . . . . . . . . . 350 v-mhz |v h Cv in | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 v |v l Cv in | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 v internal power dissipation 2 plastic dip package (n) . . . . . . . . . . . . . . . . . . . . 1.3 watts small outline package (so) . . . . . . . . . . . . . . . . . . 0.9 watts input voltage (common mode) . . . . . . . . . . . . . . . . . . . . v s differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 1.2 v output short circuit duration . . . . . . . . . . . . . . . . . . . . . . observe power derating curves storage temperature range n, r . . . . . . . . . C65 c to +125 c operating temperature range (a grade) . . . C40 c to +85 c lead temperature range (soldering 10 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for device in free air: 8-lead plastic dip: q ja = 90 c/w 8-lead soic: q ja = 155 c/w 8-lead cerdip: q ja = 110 c/w. maximum power dissipation the maximum power that can be safely dissipated by these de- vices is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsu- lated devices is determined by the glass transition temperature of the plastic, approximately +150 c. exceeding this limit tem- porarily may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceed- ing a junction temperature of +175 c for an ex tended period can result in device failure. while the ad8036 and ad8037 are internally short circuit pro- tected, this may not be sufficient to guarantee that the maxi- mum junction temperature (+150 c) is not exceeded under all conditions. to ensure proper operation, it is necessary to ob- serve the maximum power derating curves. 2.0 0 C50 80 1.5 0.5 C40 1.0 010 C10 C20 C30 20 30 40 50 60 70 90 ambient temperature C 8 c maximum power dissipation C watts t j = +150 8 c 8-lead plastic dip package 8-lead soic package figure 2. plot of maximum power dissipation vs. temperature metalization photo dimensions shown in inches and (mm). connect substrate to Cv s . ad8036 8036 ad8037 8037 +in Cv s out Cin +v s v h v l +in Cv s out Cin +v s v h v l 45 3 2 87 2 8 7 6 6 3 45 0.050 (1.27) 0.046 (1.17) 0.050 (1.27) 0.046 (1.17) ordering guide temperature package package model range description option ad8036an C40 c to +85 c plastic dip n-8 ad8036ar C40 c to +85 c soic so-8 ad8036ar-reel C40 c to +85 c 13" tape and reel so-8 ad8036ar-reel7 C40 c to +85 c 7" tape and reel so-8 ad8036achips C40 c to +85 cdie AD8036-EB evaluation board 5962-9559701mpa C55 c to +125 c cerdip q-8 ad8037an C40 c to +85 c plastic dip n-8 ad8037ar C40 c to +85 c soic so-8 ad8037ar-reel C40 c to +85 c 13" tape and reel so-8 ad8037ar-reel7 C40 c to +85 c 7" tape and reel so-8 ad8037achips C40 c to +85 cdie ad8037-eb evaluation board warning! esd sensitive device
rev. a C4C ad8036/ad8037 +v s r l = 100 v Cv s 49.9 v v in r f 130 v v out 0.1 m f 10 m f ad8036 0.1 m f 10 m f pulse generator t r /t f = 350ps figure 3. noninverting configuration, g = +1 figure 4. large signal transient response; v o = 4 v p-p, g = +1, r f = 140 w figure 5. small signal transient response; v o = 400 mv p-p, g = +1, r f = 140 w ad8036Ctypical characteristics +v s r l = 100 v Cv s 49.9 v v in r f 130 v v out 0.1 m f 10 m f ad8036 0.1 m f 10 m f pulse generator t r /t f = 350ps +v h v l 0.1 m f 0.1 m f figure 6. noninverting clamp configuration, g = +1 figure 7. clamped large signal transient response (2 overdrive); v o = 2 v p-p, g = +1, r f = 140 w , v h = +1 v, v l = C1 v figure 8. clamped small signal transient response (2 overdrive); v o = 400 mv p-p, g = +1, r f = 140 w , v h = +0.2 v, v l = C0.2 v
ad8036/ad8037 rev. a C5C ad8037Ctypical characteristics r in +v s r l = 100 v Cv s 49.9 v v in r f 100 v v out 0.1 m f 10 m f ad8037 0.1 m f 10 m f pulse generator t r /t f = 350ps +v h v l 0.1 m f 0.1 m f figure 12. noninverting clamp configuration, g = +2 figure 13. clamped large signal transient response (2 overdrive); v o = 2 v p-p, g = +2, r f = r in = 274 w , v h = +0.5 v, v l = C0.5 v figure 14. clamped small signal transient response (2 overdrive); v o = 400 mv p-p, g = +2, r f = r in = 274 w , v h = +0.1 v, v l = C0.1 v r in +v s r l = 100 v Cv s 49.9 v v in r f 100 v v out 0.1 m f 10 m f ad8037 0.1 m f 10 m f pulse generator t r /t f = 350ps figure 9. noninverting configuration, g = +2 figure 10. large signal transient response; v o = 4 v p-p, g = +2, r f = r in = 274 w figure 11. small signal transient response; v o = 400 mv p-p, g = +2, r f = r in = 274 w
rev. a C6C ad8036/ad8037 ad8036Ctypical characteristics 200 v 140 v gain C db 102 v 49.9 v 1m frequency C hz 10m 100m 1g v o = 300mv p-p v s = 6 5v r l = 100 v C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 figure 15. ad8036 small signal frequency response, g = +1 1m 158 v 140 v 150 v 10m 100m 1g gain C db v o = 300mv p-p v s = 6 5v r l = 100 v 130 v C0.8 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 frequency C hz figure 16. ad8036 0.1 db flatness, n package (for r package add 20 w to r f ) 60 10 10k 100k 10m 1m 30 20 40 50 frequency C hz open -loop gain C db 0 C10 100m 1g 100 20 0 C20 40 60 80 C80 C100 C120 C60 C40 90 70 80 C20 phase margin C degrees gain phase figure 17. ad8036 open-loop gain and phase margin vs. frequency, r l = 100 w value of feedback resistor (r f ) C v C3db bandwidth C mhz 20 240 40 200 220 180 160 140 120 100 80 60 r package r f 130 v ad8036 v s = 6 5v r l = 100 v gain = +1 r l 49.9 v n package 400 350 300 250 200 figure 18. ad8036 small signal C3 db bandwidth vs. r f output C db 1m frequency C hz 10m 100m 1g 250 v r f = 50 v to 250 v by 50 v 50 v v s = 6 5v v o = 2.5v p-p r l = 100 v C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 figure 19. ad8036 large signal frequency response, g = +1 frequency C hz gain C db 1m 10m 100m 1g 100k v s = 6 5v v o = 300mv p-p r l = 100 v C8 C7 C6 C5 C4 C3 C2 C1 0 1 2 140 v v h 100 v v l (v in ) (v o ) 1v ad8036 figure 20. ad8036 clamp input bandwidth, v h , v l
ad8036/ad8037 rev. a C7C C30 C130 100k 100m 10m 1m 10k C70 C50 C110 C90 frequency C hz harmonic distortion C dbc v o = 2v p-p v s = 6 5v r l = 500 v g = +1 2nd harmonic 3rd harmonic figure 21. ad8036 harmonic distortion vs. frequency, r l = 500 w C30 C130 100k 100m 10m 1m 10k C70 C50 C110 C90 frequency C hz harmonic distortion C dbc v o = 2v p-p v s = 6 5v r l = 100 v g = +1 2nd harmonic 3rd harmonic figure 22. ad8036 harmonic distortion vs. frequency, r l = 100 w 50 30 10 100 20 40 frequency C mhz intercept C +dbm 60 20 40 80 60 figure 23. ad8036 third order intercept vs. frequency diff gain C % 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th diff phase C degrees 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.04 0.02 0.00 C0.02 C0.04 0.04 0.02 0.00 C0.02 C0.04 0.06 C0.06 figure 24. ad8036 differential gain and phase error, g = +1, r l = 150 w , f = 3.58 mhz settling time C ns 0 5 10 15 20 25 30 35 40 45 error C % C0.05 C0.04 C0.03 C0.02 C0.01 0 0.01 0.02 0.03 0.04 0.05 figure 25. ad8036 short-term settling time to 0.01%, 2 v step, g = +1, r l = 100 w settling time - m s 0 2 4 6 8 10 12 14 16 18 error C % C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 figure 26. ad8036 long-term settling time, 2 v step, g = +1, r l = 100 w
rev. a C8C ad8036/ad8037 1m frequency C hz 475 174 374 10m 100m 1g v o = 300mv p-p v s = 6 5v r l = 100 v 274 gain C db C2 C1 0 1 2 3 4 5 6 7 8 figure 27. ad8037 small signal frequency response, g = +2 301 224 274 v o = 3.00mv p-p v s = 6 5v r l = 100 v 249 1m frequency C hz 10m 100m 1g gain C db C0.8 C0.7 C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 figure 28. ad8037 0.1 db flatness, n package (for r package add 20 w to r f ) C5 65 25 C15 10k 100k 1g 100m 10m 1m 35 45 55 5 15 frequency C hz 60 20 30 40 50 C10 0 10 open -loop gain C db C50 C250 0 50 100 C200 C150 C100 phase margin C degrees gain phase figure 29. ad8037 open-loop gain and phase margin vs. frequency, r l = 100 w ad8037Ctypical characteristics 200 150 100 550 500 450 400 350 300 250 200 150 250 300 350 value of r f ,r in C v C3db bandwidth C mhz v s = 6 5v r l = 100 v gain = +2 r f ad8037 r l r in 100 v 49.9 v n package r package figure 30. ad8037 small signal C3 db bandwidth vs. r f , r in r f = 475 v rf = 75 v to 475 v by 100 v v o = 3.5 v p-p v s = 6 5v r l = 100 v r f = 75 v 1m frequency C hz 10m 100m 1g gain C db C2 C1 0 1 2 3 4 5 6 7 8 figure 31. ad8037 large signal frequency response, g = +2 frequency C hz gain C db v s = 6 5v v o = 300mv p-p r l = 100 v 274 v v h 100 v ad8037 v l (v in ) (v o ) 1v 274 v 100k 1m 10m 100m 1g C2 C1 0 1 2 3 4 5 6 7 8 figure 32. ad8037 clamp input bandwidth, v h , v l
ad8036/ad8037 rev. a C9C C30 C130 100k 100m 10m 1m 10k C70 C50 C110 C90 frequency C hz harmonic distortion C dbc v o = 2v p-p v s = 6 5v r l = 500 v g = +2 2nd harmonic 3rd harmonic figure 33. ad8037 harmonic distortion vs. frequency, r l = 500 w C30 C130 100k 100m 10m 1m 10k C70 C50 C110 C90 frequency C hz harmonic distortion C dbc v o = 2v p-p v s = 6 5v r l = 100 v g = +2 2nd harmonic 3rd harmonic figure 34. ad8037 harmonic distortion vs. frequency, r l = 100 w 50 30 10 100 20 40 frequency C mhz intercept C +dbm 60 20 40 80 60 figure 35. ad8037 third order intercept vs. frequency diff gain C % 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th diff phase C degrees 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 0.03 0.02 0.01 0.00 C0.01 C0.02 C0.03 0.03 0.02 0.01 0.00 C0.01 C0.02 C0.03 figure 36. ad8037 differential gain and phase error g = +2, r l = 150 w , f = 3.58 mhz settling time C ns 0 5 10 15 20 25 30 35 40 45 error C % C0.05 C0.04 C0.03 C0.02 C0.01 0 C0.01 C0.02 C0.03 C0.04 C0.05 figure 37. ad8037 short-term settling time to 0.01%, 2 v step, g = +2, r l = 100 w settling time C m s 0 2 4 6 8 10 12 14 16 18 error C % C0.6 C0.5 C0.4 C0.3 C0.2 C0.1 0 0.1 0.2 0.3 0.4 figure 38. ad8037 long-term settling time 2 v step, r l = 100 w
rev. a C10C 100 10k 1k 10 frequency C hz v s = 6 5v input noise voltage C nv/ hz 32 28 24 20 16 12 8 4 100k figure 39. ad8036 noise vs. frequency 80 70 60 50 40 30 20 10 0 75 65 55 45 35 25 15 5 10k 100k 1g 100m 10m 1m frequency C hz psrr C db Cpsrr +psrr figure 40. ad8036 psrr vs. frequency 100 90 80 70 60 50 40 30 20 100k 1g 100m 10m 1m frequency C hz cmrr C db v s = 6 5v d v cm = 1v r l = 100 v figure 41. ad8036 cmrr vs. frequency ad8036/ad8037Ctypical characteristics 100 100k 10k 1k 10 frequency C hz v s = 6 5v input noise voltage C nv/ hz 17 15 13 11 9 7 5 3 figure 42. ad8037 noise vs. frequency 80 70 60 50 40 30 20 10 0 75 65 55 45 35 25 15 5 10k 100k 1g 100m 10m 1m frequency C hz psrr C db Cpsrr +psrr figure 43. ad8037 psrr vs. frequency 100 90 80 70 60 50 40 30 20 100k 1g 100m 10m 1m frequency C hz cmrr C db v s = 6 5v d v cm = 1v r l = 100 v figure 44. ad8037 cmrr vs. frequency
ad8036/ad8037 rev. a C11C 0.1m frequency C hz 1.0m 100m 10m 300m r out C v v s = 6 5v g = +1 1k 100 10 1 0.1 0.01 figure 45. ad8036 output resistance vs. frequency 0.1m frequency C hz 1.0m 100m 10m 300m r out C v v s = 6 5v g = +2 1k 100 10 1 0.1 0.01 figure 46. ad8037 output resistance vs. frequency output swing C volts junction temperature C 8 c Cv out +v out r l =150 r l = 50 Cv out +v out 4.2 4.1 4.0 3.9 3.8 3.7 3.6 3.5 3.4 C60 C40 C20 0 20 40 60 80 100 120 140 figure 47. ad8036/ad8037 output swing vs. temperature 1400 1300 1200 1100 1000 900 800 700 600 500 400 C60 C40 C20 0 20 40 60 80 100 120 140 Ca ol +a ol Ca ol +a ol ad8036 ad8037 junction temperature C 8 c open -loop gain C v/ v figure 48. open-loop gain vs. temperature C60 C40 C20 0 20 40 60 80 100 120 140 psrr C db junction temperature C 8 c Cpsrr ad8037 ad8036 ad8037 ad8036 +psrr +psrr Cpsrr 74 72 70 68 66 64 62 60 figure 49. psrr vs. temperature 15 25 35 45 55 65 75 85 95 cmrr C db junction temperature C 8 c d v cm = 2v 96 95 94 93 92 91 90 89 88 figure 50. ad8036/ad8037 cmrr vs. temperature
rev. a C12C ad8036/ad8037Ctypical characteristics C60 C40 C20 0 20 40 60 80 100 120 140 supply current C ma junction temperature C 8 c ad8036, v s = 6 6v ad8036, v s = 6 5v ad8037, v s = 6 6v ad8037, v s = 6 5v 24 23 22 21 20 19 18 17 figure 51. supply current vs. temperature C60 C40 C20 0 20 40 60 80 100 120 140 junction temperature C 8 c v s = 6 6v v s = 6 5v v s = 6 6v v s = 6 5v input offset voltage C mv ad8037 ad8036 C2.50 C2.25 C2.00 C1.75 C1.50 C1.25 C1.00 C0.75 C0.50 figure 52. input offset voltage vs. temperature input offset voltage C mv count 3 wafer lots count = 632 freq. dist C6C5C4C3C2C101234 44 40 36 32 28 24 20 16 12 8 4 0 figure 53. ad8036 input offset voltage distribution C60 C40 C20 0 20 40 60 80 100 120 140 junction temperature C 8 c ad8037 ad8036 ad8036 short circuit current C ma ad8037 sink source 270 260 250 240 230 220 210 200 figure 54. short circuit current vs. temperature C60 C40 C20 0 20 40 60 80 100 120 140 junction temperature C 8 c Cib input bias current C m a ad8037 ad8036 +ib Cib +ib 4.5 4.0 3.5 3.0 2.5 2.0 1.5 figure 55. input bias current vs. temperature input offset voltage C mv count 3 wafer lots count = 853 freq. dist 48 44 40 36 32 28 24 20 16 12 8 4 0 C4.5 C4.0 C3.5 C3.0 C2.5 C2.0 C1.5 C1.0 C0.5 0 0.5 figure 56. ad8037 input offset voltage distribution
rev. a C13C 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 C80 C75 C70 C65 C60 C55 C50 C45 C40 C35 C30 absolute value of output voltage C volts harmonic distortion C dbc v h +1v +0.5v v l C1v C0.5v g +1v +2v ad8036 ad8037 ad8037 3rd harmonic ad8036 3rd harmonic ad8036 2nd harmonic ad8037 2nd harmonic figure 60. harmonic distortion as output approaches clamp voltage; v o = 2 v p-p, r l = 100 v , f = 20 mhz C5 C4 C3 C2 C1 0 1 2 3 4 5 input clamp voltage (v h ,v l ) C volts i bh i bl positive i bh , i bl denotes current flow into clamp inputs v h , v l clamp input bias current C m a 80 60 40 20 0 C20 C40 C60 C80 figure 61. ad8036/ad8037 clamp input bias current vs. input clamp voltage ref +2v +1v 0v figure 62. ad8037 clamp overdrive (2x) recovery v cl = C3v C3 C2 C1 0 1 2 3 output voltage C volts ad8036, a cl = +1 ad8037, a cl = +2 ad8036 ad8037 input error voltage C mv v cl = C2v v cl = C1v v ch = +1v v ch = +2v v ch = +3v 20 15 10 5 0 C5 C10 C15 C20 figure 57. input error voltage vs. clamped output voltage 1.0 C0.8 C1.0 0.8 0.6 0.4 0.2 0.0 C0.2 C0.4 C0.6 input voltage a v C volts nonlinearity C mv v h = + 1v v l = C 1v 20 15 10 5 0 C5 C10 C15 C20 figure 58. ad8036/ad8037 nonlinearity near clamp voltage ref +2v +1v 0v figure 59. ad8036 clamp overdrive (2x) recovery clamp characteristicsCad8036/ad8037
ad8036/ad8037Cclamp characteristics rev. a C14C error C % 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 settling time C ns 0 102030405060708090 figure 66. ad8037 clamp settling (0.1%), v h = +0.5 v, v l = C0.5 v, 2 overdrive 0 5 10 15 20 25 30 35 40 settling time C ns error C % 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 figure 67. ad8037 clamp recovery settling time (high), from +2 overdrive to 0 v 0 5 10 15 20 25 30 35 40 settling time C ns error C % 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 figure 68. ad8037 clamp recovery settling time (low), from C2 overdrive to 0 v error C % settling time C ns 0 102030405060708090 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 figure 63. ad8036 clamp settling (0.1%), v h = +1 v, v l = C1 v, 2 overdrive 0 5 10 15 20 25 30 35 40 settling time C ns error C % 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 figure 64. ad8036 clamp recovery settling time (high), from +2 overdrive to 0 v 0 5 10 15 20 25 30 35 40 settling time C ns error C % 0.5 0.4 0.3 0.2 0.1 0 C0.1 C0.2 C0.3 C0.4 C0.5 figure 65. ad8036 clamp recovery settling time (low), from C2 overdrive to 0 v
ad8036/ad8037 rev. a C15C theory of operation general the ad8036 and ad8037 are wide bandwidth, voltage feed- back clamp amplifiers. since their open-loop frequency re- sponse follows the conventional 6 db/octave roll-off, their gain bandwidth product is basically constant. increasing their closed-loop gain results in a corresponding decrease in small sig- nal bandwidth. this can be observed by noting the bandwidth specification, between the ad8036 (gain of 1) and ad8037 (gain of 2). the ad8036/ad8037 typically maintain 65 de- grees of phase margin. this high margin minimizes the effects of signal and noise peaking. while the ad8036 and ad8037 can be used in either an invert- ing or noninverting configuration, the clamp function will only work in the noninverting mode. as such, this section shows con- nections only in the noninverting configuration. applications that require an inverting configuration will be discussed in the applications section. in applications that do not require clamp- ing, pins 5 and 8 (respectively v l and v h ) may be left floating. see input clamp amp operation and applications sections otherwise. feedback resistor choice the value of the feedback resistor is critical for optimum perfor- mance on the ad8036 (gain +1) and less critical as the gain in- creases. therefore, this section is specifically targeted at the ad8036. at minimum stable gain (+1), the ad8036 provides optimum dynamic performance with r f = 140 w . this resistor acts only as a parasitic suppressor against damped rf oscillations that can occur due to lead (input, feedback) inductance and parasitic capacitance. this value of r f provides the best combination of wide bandwidth, low parasitic peaking, and fast settling time. in fact, for the same reasons, a 100C130 w resistor should be placed in series with the positive input for other ad8036 non- inverting configurations. the correct connection is shown in figure 69. r f 100 - 130 v r term r f r g g = 1+ r g v h v l +v s Cv s v in v out 0.1 m f 10 m f 0.1 m f 10 m f ad8036/ ad8037 figure 69. noninverting operation for general voltage gain applications, the amplifier bandwidth can be closely estimated as: f 3 db @ w o 2 p 1 + r f r g ? ? ? ? ? ? this estimation loses accuracy for gains of +2/C1 or lower due to the amplifiers damping factor. for these low gain cases, the bandwidth will actually extend beyond the calculated value (see closed-loop bw plots, figures 15 and 27). pulse response unlike a traditional voltage feedback amplifier, where the slew speed is dictated by its front end dc quiescent current and gain bandwidth product, the ad8036 and ad8037 provide on de- mand current that increases proportionally to the input step signal amplitude. this results in slew rates (1200 v/ m s) compa- rable to wideband current feedback designs. this, combined with relatively low input noise current (2.1 pa/ ? hz ), gives the ad8036 and ad8037 the best attributes of both voltage and current feedback amplifiers. large signal performance the outstanding large signal operation of the ad8036 and ad8037 is due to a unique, proprietary design architecture. in order to maintain this level of performance, the maximum 350 v-mhz product must be observed, (e.g., @ 100 mhz, v o 3.5 v p-p). power supply and input clamp bypassing adequate power supply bypassing can be critical when optimiz- ing the performance of a high frequency circuit. inductance in the power supply leads can form resonant circuits that produce peaking in the amplifiers response. in addition, if large current transients must be delivered to the load, then bypass capacitors (typically greater than 1 m f) will be required to provide the best settling time and lowest distortion. a parallel combination of at least 4.7 m f, and between 0.1 m f and 0.01 m f, is recommended. some brands of electrolytic capacitors will require a small series damping resistor ? 4.7 w for optimum results. when the ad8036 and ad8037 are used in clamping mode, and a dc voltage is connected to clamp inputs v h and v l , a 0.1 m f bypassing capacitor is required between each input pin and ground in order to maintain stability. driving capacitive loads the ad8036 and ad8037 were designed primarily to drive nonreactive loads. if driving loads with a capacitive component is desired, the best frequency response is obtained by the addi- tion of a small series resistance as shown in figure 70. the ac- companying graph shows the optimum value for r series vs. capacitive load. it is worth noting that the frequency response of the circuit when driving large capacitive loads will be dominated by the passive roll-off of r series and c l . for capacitive loads of 6 pf or less, no r series is necessary. r l 1k v r f r in r series c l ad8036/ ad8037 r in figure 70. driving capacitive loads
rev. a C16C ad8036/ad8037 operation of the ad8036 for negative input voltages and nega- tive clamp levels on v l is similar, with comparator c l control- ling s1. since the comparators see the voltage on the +v in pin as their common reference level, then the voltage v h and v l are defined as high or low with respect to +v in . for example, if v in is set to zero volts, v h is open, and v l is +1 v, compara- tor c l will switch s1 to c, so the ad8036 will buffer the voltage on v l and ignore +v in . the performance of the ad8036 and ad8037 closely matches the ideal just described. the comparators threshold extends from 60 mv inside the clamp window defined by the voltages on v l and v h to 60 mv beyond the windows edge. switch s1 is implemented with current steering, so that a1s +input makes a continuous transition from say, v in to v h as the input voltage traverses the comparators input threshold from 0.9 v to 1.0 v for v h = 1.0 v. the practical effect of these nonidealities is to soften the transition from amplification to clamping modes, without com- promising the absolute clamp limit set by the clampin cir- cuit. figure 73 is a graph of v out vs. v in for the ad8036 and a typical output clamp amplifier. both amplifiers are set for g = +1 and v h = +1 v. the worst case error between v out (ideally clamped) and v out (actual) is typically 18 mv times the amplifier closed-loop gain. this occurs when v in equals v h (or v l ). as v in goes above and/or below this limit, v out will settle to within 5 mv of the ideal value. in contrast, the output clamp amplifiers transfer curve typically will show some compression starting at an input of 0.8 v, and can have an output voltage as far as 200 mv over the clamp limit. in addition, since the output clamp in effect causes the amplifier to operate open loop in clamp mode, the amplifiers output impedance will increase, potentially causing additional errors. the ad8036s and ad8037s clampin input clamp architec- ture works only for noninverting or follower applications and, since it operates on the input, the clamp voltage levels v h and v l , and input error limits will be multiplied by the amplifiers a b c s1 r f 140 v a b c 0 1 0 1 0 0 0 0 1 s1 v in > v h v l v in v h v in < v l Cv in +v in v h v l v out +1 +1 +1 c h c l a1 a2 +1 figure 72. ad8036/ad8037 clamp amp system 0 5 10 15 20 25 r series C v c l C pf 40 30 20 10 figure 71. recommended r series vs. capacitive load input clamping amplifier operation the key to the ad8036 and ad8037s fast, accurate clamp and amplifier p erformance is their unique patent pen ding clampin input clamp architecture. this new design reduces clamp errors by more than 10 over previous output clamp based circuits, as well as substantially increasing the bandwidth, precision and versatility of the clamp inputs. figure 72 is an idealized block diagram of the ad8036 con- nected as a unity gain voltage follower. the primary signal path comprises a1 (a 1200 v/ m s, 240 mhz high voltage gain, differ- ential to single-ended amplifier) and a2 (a g = +1 high current gain output buffer). the ad8037 differs from the ad8036 only in that a1 is optimized for closed-loop gains of two or greater. the clampin section is comprised of comparators c h and c l , which drive switch s1 through a decoder. the unity-gain buffers in series with +v in , v h , and v l inputs isolate the input pins from the comparators and s1 without reducing bandwidth or precision. the two comparators have about the same bandwidth as a1 (240 mhz), so they can keep up with signals within the useful bandwidth of the ad8036. to illustrate the operation of the clampin circuit, consider the case where v h is referenced to +1 v, v l is open, and the ad8036 is set for a gain of +1, by connecting its output back to its inverting input through the rec- ommended 140 w feedback resistor. note that the main signal path always operates closed loop, since the clampin circuit only affects a1s noninverting input. if a 0 v to +2 v voltage ramp is applied to the ad8036s +v in for the connection just described, v out should track +v in per- fectly up to +1 v, then should limit at exactly +1 v as +v in con- tinues to +2 v. in practice, the ad8036 comes close to this ideal behavior. as the +v in input voltage ramps from zero to 1 v, the output of the high limit comparator c h starts in the off state, as does the out- put of c l . when +v in just exceeds v in (ideally, by say 1 m v, practically by about 18 mv), c h changes state, switching s1 from a to b reference level. since the + input of a1 is now connected to v h , further increases in +v in have no effect on the ad8036s output voltage. in short, the ad8036 is now operat- ing as a unity-gain buffer for the v h input, as any variation in v h , for v h > 1 v, will be faithfully reproduced at v out .
ad8036/ad8037 rev. a C17C closed-loop gain at the output. for instance, to set an output limit of 1 v for an ad8037 operating at a gain of 3.0, v h and v l would need to be set to +0.333 v and C0.333 v, respectively. the only restriction on using the ad8036s and ad8037s +v in , v l , v h pins as inputs is that the maximum voltage differ- ence between +v in and v h or v l should not exceed 6.3 v, and all three voltages be within the supply voltage range. for ex- ample, if v l is set at C3 v, then v in should not exceed +3.3 v. 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 input voltage C +v in 1.6 0.6 1.2 0.8 1.0 1.4 output voltage C v out ad8036 output clamp amp clamp error C 25mv ad8036 clamp error C >200mv output clamp figure 73. output clamp error vs. input clamp error ad8036/ad8037 applications the ad8036 and ad8037 use a unique input clamping circuit to perform the clamping function. as a result, they provide the clamping function better than traditional output clamping de- vices and provide additional flexibility to perform other unique applications. there are, however, some restrictions on circuit configurations; and some calculations need to be performed in order to figure the clamping level, as a result of clamping being performed at the input stage. the major restriction on the clamping feature of the ad8036/ ad8037 is that clamping occurs only when using the amplifiers in the noninverting mode. to clamp in an inverting circuit, an additional inverting gain stage is required. another restriction is that v h be greater than v l , and that each be within the output voltage range of the amplifier ( 3.9 v). v h can go below ground and v l can go above g round as long as v h is kept higher than v l . unity gain clamping the simplest circuit for calculating the clamp levels is a unity gain follower as shown in figure 74. in this case, the ad8036 should be used since it is compensated for noninverting unity gain. this circuit will clamp at an upper voltage set by v h (the voltage applied to pin 8) and a lower voltage set by v l (the voltage ap- plied to pin 5). clamping with gain figure 75 shows an ad8037 configured for a noninverting gain of two. the ad8037 is used in this circuit since it is compen- sated for gains of two or greater and provides greater band- width. in this case, the high clamping level at the output will +5v r f 140 v C5v 130 v v h v l v in v out 0.1 m f 10 m f 0.1 m f ad8036 0.1 m f10 m f v h 0.1 m f v l figure 74. unity gain noninverting clamp occur at 2 v h and the low clamping level at the output will be 2 v l . the equations governing the output clamp levels in cir- cuits configured for noninverting gain are: v ch = g v h v cl = g v l where: v ch is the high output clamping level v cl is the low output clamping level g is the gain of the amplifier configuration v h is the high input clamping level (pin 8) v l is the low input clamping level (pin 5) *amplifier offset is assumed to be zero. +5v r f 274 v C5v 100 v v h v l v in v out 0.1 m f 10 m f 0.1 m f ad8037 0.1 m f10 m f v h 0.1 m f v l r g 274 v 49.9 v figure 75. gain of two noninverting clamp
rev. a C18C ad8036/ad8037 clamping with an offset some op amp circuits are required to operate with an offset voltage. these are generally configured in the inverting mode where the offset voltage can be summed in as one of the inputs. since ad8036/ad8037 clamping does not function in the in- verting mode, it is not possible to clamp with this configuration. figure 76 shows a noninverting configuration of an ad8037 that provides clamping and also has an offset. the circuit shows the ad8037 as a driver for an ad9002, an 8-bit, 125 msps a/d converter and illustrates some of the considerations for us- ing an ad8037 with offset and clamping. the analog input range of the ad9002 is from ground to C2 v. the input should not go more than 0.5 v outside this range in order to prevent disruptions to the internal workings of the a/d and to avoid drawing excess current. these requirements make the ad8037 a prime candidate for signal conditioning. when an offset is added to a noninverting op amp circuit, it is fed in through a resistor to the inverting input. the result is that the op amp must now operate at a closed-loop gain greater than unity. for this circuit a gain of two was chosen which allows the use of the ad8037. the feedback resistor, r2, is set at 301 w for optimum performance of the ad8037 at a gain of two. there is an interaction between the offset and the gain, so some calculations must be performed to arrive at the proper values for r1 and r3. for a gain of two the parallel combination of resis- tors r1 and r3 must be equal to the feedback resistor r2. thus r 1 r 3/ r 1 + r 3 = r 2 = 301 w the reference used to provide the offset is the ad780 whose output is 2.5 v. this must be divided down to provide the 1 v offset desired. thus 2.5 v r 1/( r 1 + r 3) = 1 v when the two equations are solved simultaneously we get r1 = 499 w and r3 = 750 w (using closest 1% resistor values in all cases). this positive 1 v offset at the input translates to a C1 v offset at the output. the usable input signal swing of the ad9002 is 2 v p-p. this is centered about the C1 v offset making the usable signal range from 0 v to C2 v. it is desirable to clamp the input signal so that it goes no more than 100 mv outside of this range in either direction. thus, the high clamping level should be set at +0.1 v and the low clamping level should be set at C2.1 v as seen at the input of the ad9002 (output of ad8037). because the clamping is done at the input stage of the ad8037, the clamping level as seen at the output is affected by not only the gain of the circuit as previously described, but also by the offset. thus, in order to obtain the desired clamp levels, v h must be biased at +0.55 v while v l must be biased at C0.55 v. the clamping levels as seen at the output can be calculated by the following: v ch = v off + g v h v cl = v off + g v l where v off is the offset voltage that appears at the output. the resistors used to generate the voltages for v h and v l should be kept to a minimum in order to reduce errors due to clamp bias current. this current is dependent on v h and v l (see fig- ure 61) and will create a voltage drop across whatever resistance is in series with each clamp input. this extra error voltage is multiplied by the closed-loop gain of the amplifier and can be substantial, especially in high closed-loop gain configurations. a 0.1 m f bypass capacitor should be placed between input clamp pins v h and v l and ground to ensure stable operation. the 1n5712 schottky diode is used for protection from forward biasing the substrate diode in the ad9002 during power-up transients. programmable pulse generator the ad8036/ad8037s clamp output can be set accurately and has a well controlled flat level. this along with wide bandwidth and high slew rate make them very well suited for programmable level pulse generators. figure 77 is a schematic for a pulse generator that can directly accept ttl generated timing signals for its input and generate pulses at the output up to 24 v p-p with 2500 v/ m s slew rate. the output levels can be programmed to anywhere in the range C12 v to +12 v. 100 v C0.5v to +0.5v C2v to 0v clamping range C2.1v to +0.1v 2.5v +5v 10f C5.2v 1n5712 +5v r2 301 v C5v 100 v v h v l v in 0.1 m f10 m f 0.1 m f ad8037 0.1 m f 10 m f r1 499 v 49.9 v 806 v +5v 0.1 m f 806 v C5v 100 v r3 750 v 0.1 m f 0.1 m f ad780 49.9 v ad9002 v in = C2v to 0v substrate diode 0.1 m f figure 76. gain of two, noninverting with offset ad8037 driving an ad90028-bit, 125 msps a/d converter
ad8036/ad8037 rev. a C19C the circuit uses an ad8037 operating at a gain of two with an ad811 to boost the output to the 12 v range. the ad811 was chosen for its ability to operate with 15 v supplies and its high slew rate. r1 and r2 act as a level shifter to make the ttl signal levels be approximately symmetrical above and below ground. this en- sures that both the high and low logic levels will be clamped by the ad8037. for well controlled signal levels in the output pulse, the high and low output levels should result from the clamping action of the ad8037 and not be controlled by either the high or low logic levels passing through a linear amplifier. for good rise and fall times at the output pulse, a logic family with high speed edges should be used. the high logic levels are clamped at two times the voltage at v h , while the low logic levels are clamped at two times the voltage at v l . the output of the ad8037 is amplified by the ad811 operating at a gain of 5. the overall gain of 10 will cause the high output level to be 10 times the voltage at v h , and the low output level to be 10 times the voltage at v l . high speed, full-wave rectifier the clamping inputs are additional inputs to the input stage of the op amp. as such they have an input bandwidth comparable to the amplifier inputs and lend themselves to some unique functions when they are driven dynamically. figure 78 is a schematic for a full-wave rectifier, sometimes called an absolute value generator. it works well up to 20 mhz and can operate at significantly higher frequencies with some degradation in performance. the distortion performance is sig- nificantly better than diode based full-wave rectifiers, especially at high frequencies. v out = v in +5v r f 274 v C5v 100 v v h v l v in 0.1 m f10 m f ad8037 0.1 m f 10 m f r g 274 v figure 78. full-wave rectifier ttl in +15v pulse out v h 3 10 v l 3 10 C15v +5v 274 v C5v 100 v v h v l 0.1 m f 10 m f 0.1 m f ad8037 0.1 m f10 m f v h 0.1 m f v l 274 v 1.3k v 200 v 100 v ad811 C15v 0.1 m f10 m f 0.1 m f 10 m f 604 v 150 v figure 77. programmable pulse generator the circuit is configured as an inverting amplifier with a gain of one. the input drives the inverting amplifier and also directly drives v l , the lower level clamping input. the high level clamp- ing input, v h , is left floating and plays no role in this circuit. when the input is negative, the amplifier acts as a regular unity- gain inverting amplifier and outputs a positive signal at the same amplitude as the input with opposite polarity. v l is driven nega- tive by the input, so it performs no clamping action, because the positive output signal is always higher than the negative level driving v l . when the input is positive, the output result is the sum of two separate effects. first, the inverting amplifier multiplies the in- put by C1 because of its unity-gain inverting configuration. this effectively produces an offset as explained above, but with a dy- namic level that is equal to C1 times the input. second, although the positive input is grounded (through 100 w ), the output is clamped at two times the voltage applied to v l (a positive, dynamic voltage in this case). the factor of two is be- cause the noise gain of the amplifier is two. the sum of these two actions results in an output that is equal to unity times the input signal for positive input signals, see fig- ure 79. for a input/output scope photo with an input signal of 20 mhz and amplitude 1 v, see figure 80. input full wave rectified output lower clamping level with no neg input output lower clamping level C1 3 input figure 79.
rev. a C20C ad8036/ad8037 figure 80. full-wave rectifier scope thus for either positive or negative input signals, the output is unity times the absolute value of the input signal. the circuit can be easily configured to produce the negative absolute value of the input by applying the input to v h instead of v l . the circuit can get to within about 40 mv of ground during the time when the input crosses zero. this voltage is fixed over a wide frequency range and is a result of the switching between the conventional op amp input and the clamp input. but be- cause there are no diodes to rapidly switch from forward to re- verse bias, the performance far exceeds that of diode based full wave rectifiers. the 40 mv offset mentioned can be removed by adding an off- set to the circuit. a 27.4 k w input resistor to the inverting input will have a gain of 0.01, while changing the gain of the circuit by only 1%. a plus or minus 4 v dc level (depending on the polar- ity of the rectifier) into this resistor will compensate for the offset. full wave rectifiers are useful in many applications including am signal detection, high frequency ac voltmeters and various arithmetic operations. amplitude modulator in addition to being able to be configured as an amplitude de- modulator (am detector), the ad8037 can also be configured as an amplitude modulator as shown in figure 81. carrier in v h am out modulation in +5v r f 274 v C5v 100 v v h v l 0.1 m f10 m f ad8037 0.1 m f 10 m f r g 274 v figure 81. amplitude modulator the positive input of the ad8037 is driven with a square wave of sufficient amplitude to produce clamping action at both the high and low levels. this is the higher frequency carrier signal. the modulation signal is applied to both the input of a unity gain inverting amplifier and to v l , the lower clamping input. v h is biased at +0.5 v dc. to understand the circuit operation, it is helpful to first con- sider a simpler circuit. if both v l and v h were dc biased at C0.5 v and the carrier and modulation inputs driven as above, the output would be a 2 v p-p square wave at the carrier fre- quency riding on a waveform at the modulating frequency. the inverting input (modulation signal) is creating a varying offset to the 2 v p-p square wave at the output. both the high and low levels clamp at twice the input levels on the clamps because the noise gain of the circuit is two. when v l is driven by the modulation signal instead of being held at a dc level, a more complicated situation results. the re- sulting waveform is composed of an upper envelope and a lower envelope with the carrier square wave in between. the upper and lower envelope waveforms are 180 out of phase as in a typical am waveform. the upper envelope is produced by the upper clamp level being offset by the waveform applied to the inverting input. this offset is the opposite polarity of the input waveform because of the inverting configuration. the lower envelope is produced by the sum of two effects. first, it is offset by the waveform applied to the inverting input as in the case of the simplified circuit above. the polarity of this off- set is in the same direction as the upper envelope. second, the output is driven in the opposite direction of the offset at twice the offset voltage by the modulation signal being applied to v l . this results from the noise gain being equal to two, and since there is no inversion in this connection, it is opposite polarity from the offset. the result at the output for the lower envelope is the sum of these two effects, which produces the lower envelope of an am- plitude modulated waveform. see figure 82. figure 82. am waveform the depth of modulation can be modified in this circuit by changing the amplitude of the modulation signal. this changes the amplitude of the upper and lower envelope waveforms. the modulation depth can also be changed by changing the dc bias applied to v h . in this case the amplitudes of the upper and lower envelope waveforms stay constant, but the spacing be- tween them changes. this alters the ratio of the envelope ampli- tude to the amplitude of the overall waveform.
ad8036/ad8037 rev. a C21C layout considerations the specified high speed performance of the ad8036 and ad8037 requires careful attention to board layout and compo- nent selection. proper rf design techniques and low pass para- sitic component selection are mandatory. the pcb should have a ground plane covering all unused por- tions of the component side of the board to provide a low im- pedance path. the ground plane should be removed from the area near the input pins to reduce stray capacitance. chip capacitors should be used for supply and input clamp by- passing (see figure 83). one end should be connected to the ground plane and the other within 1/8 inch of each power and clamp pin. an additional large (0.47 m fC10 m f) tantalum elec- trolytic capacitor should be connected in parallel, though not necessarily so close, to supply current for fast, large signal changes at the output. the feedback resistor should be located close to the inverting input pin in order to keep the stray capacitance at this node to a minimum. capacitance variations of less than 1 pf at the in- verting input will significantly affect high speed performance. stripline design techniques should be used for long signal traces (greater than about 1 inch). these should be designed with a characteristic impedance of 50 w or 75 w and be properly termi- nated at each end. evaluation board an evaluation board for both the ad8036 and ad8037 is avail- able that has been carefully laid out and tested to demonstrate that the specified high speed performance of the device can be realized. for ordering information, please refer to the ordering guide. the layout of the evaluation board can be used as shown or serve as a guide for a board layout. in r o 1k v v out 0.1 m f ad8036/ ad8037 v h 0.1 m f v l r s Cv s +v s Cv s +v s r g r f 1k v Cv s +v s r t noninverting configuration c5 10 m f +v s Cv s c3 0.1 m f c1 0.01 m f c6 10 m f c4 0.1 m f c2 0.01 m f optional supply bypassing figure 83. noninverting configurations for evaluation boards table i. ad8036a ad8037a gain gain component +1 +2 +10 +100 +2 +10 +100 r f 140 w 274 w 2 k w 2 k w 274 w 2 k w 2 k w r g 274 w 221 w 20.5 w 274 w 221 w 20.5 w r o (nominal) 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w r s 130 w 100 w 100 w 100 w 100 w 100 w 100 w r t (nominal) 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w 49.9 w small signal bw (mhz) 240 90 10 1.3 275 21 3
rev. a C22C ad8036/ad8037 figure 84. evaluation board silkscreen (top) figure 85. evaluation board silkscreen (bottom) figure 86. board layout (solder side) figure 87. board layout (component side)
ad8036/ad8037 rev. a C23C outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n package) seating plane 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 8 14 5 pin 1 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) bsc 0.430 (10.92) 0.348 (8.84) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 8-lead plastic soic (so package) 85 4 1 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0500 (1.27) bsc 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 8 0 8 0.0196 (0.50) 0.0099 (0.25) 3 45 8 8-lead cerdip (q package) 1 4 85 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.055 (1.4) max 0.100 (2.54) bsc 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) seating plane 0.200.(5.08) max 0.405 (10.29) max 0.150 (3.81) min 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) printed in u.s.a. c1980aC0C9/99

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